Memory system executing flush command and method of controlling nonvolatile memory upon receiving flush command

A memory system comprising:

• a nonvolatile memory including a plurality of memory cells, each of the plurality of memory cells being configured to store, in a nonvolatile manner, a plurality of bits of data including at least a first bit that is to be written by a first write operation and a second bit that is to be written by a second write operation, the plurality of memory cells including at least a first memory cell and a second memory cell different from the first memory cell;
• and
• a memory controller electrically coupled to the nonvolatile memory and configured to:
• execute a data erase operation to the first memory cell resulting in the first memory cell storing no valid data as the first bit or the second bit;
• execute a data erase operation to the second memory cell resulting in the second memory cell storing no valid data as the first bit or the second bit;
• write first bit data to the first memory cell as the first bit by the first write operation;
• and
• write second bit data to the second memory cell as the first bit by the first write operation,
• wherein the memory controller is further configured to:
• upon reception of a flush command from a host while the first memory cell stores the first bit data as the first bit and does not store valid data as the second bit, and the second memory cell stores the second bit data as the first bit and does not store valid data as the second bit,
• read the first bit data from the first memory cell;
• write the first bit data to the first memory cell as the second bit;
• read the second bit data from the second memory cell;
• and
• write the second bit data to the second memory cell as the second bit.

A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of memory cells, each of the plurality of memory cells being configured to store, in a nonvolatile manner, a plurality of bits of data including at least a first bit that is to be written by a first write operation and a second bit that is to be written by a second write operation, the plurality of memory cells including at least a first memory cell and a second memory cell different from the first memory cell, the method comprising:

• executing a data erase operation to the first memory cell resulting in the first memory cell storing no valid data as the first bit or the second bit;
• executing a data erase operation to the second memory cell resulting in the second memory cell storing no valid data as the first bit or the second bit;
• writing first bit data to the first memory cell as the first bit by the first write operation;
• and
• writing second bit data to the second memory cell as the first bit by the first write operation, wherein the method further comprises:
• receiving a flush command from a host;
• upon the reception of the flush command from the host while the first memory cell stores the first bit data as the first bit and does not store valid data as the second bit, and the second memory cell stores the second bit data as the first bit and does not store valid data as the second bit,
• reading the second bit data from the second memory cell;
• and
• writing the second bit data read from the second memory cell to the first memory cell as the second bit.