Artificial intelligence processing unit addressing method and artificial intelligence processing unit addressing system capable of segregating and extending memory address range

An artificial intelligence processing unit (APU) system comprising:

• an APU engine configured to perform heterogeneous devices;
• a micro-processor linked to the APU engine and configured to control the APU engine;
• a user terminal linked to the APU engine;
• and
• a dynamic random-access memory (DRAM) linked to the APU engine, the micro-processor, and the user terminal;
• wherein the micro-processor and the APU engine are disposed inside an APU, an APU address range is partitioned into a reserved address range and an extensible address range, a reserved page table is allocated to the micro-processor for executing a firmware program on the reserved address range, the micro-processor allocates N session page tables to the APU engine for executing N runtimes on the extensible address range, each runtime corresponds to its own session page table, the APU engine operates a user process of the user terminal over the N runtimes on the extensible address range, a runtime is a processing procedure executed by the APU when executing an artificial intelligence (AI) model, the extensible address range is equal to N×S, S is a maximum address range of the each runtime, and N is a positive integer.