Flash memory controller and flash memory access method

A flash memory controller for accessing a flash memory, wherein the flash memory controller comprises:

• a read-only memory for storing a program code;
• a microprocessor for executing the program code to control access to the flash memory;
• and
• a decoder for performing decoding operation based on an N×M base matrix of a low-density parity-check (LDPC) code to decode read information from the flash memory, wherein the decoder comprises:
• a controller for transforming the base matrix into a compressed matrix of size N×S, wherein S is less than M, each element in each column of the compressed matrix is associated with a group number, and the elements from the same column of the base matrix are assigned the same group number;
• a variable node (VN) unit, coupled to the controller and comprises a plurality of first input terminals;
• a check node (CN) unit, coupled to the VN unit, wherein, in an iterative manner, the VN unit updates a plurality of V2C messages to the CN unit and the CN unit updates a plurality of C2V messages to the VN unit in order to finally generate a decoding result;
• wherein during each decoding cycle of an iteration, the VN unit receives a column of the compressed matrix through the plurality of first input terminals as input values, the elements of the column of the compressed matrix are ordered according to the group number before being input to the plurality of first input terminals.