Memory system generating parity check codes using a randomizer

A method, comprising:

• generating, by using a randomizer, a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule;
• receiving data to be stored in a memory device;
• generating one or more parity check codes according to the pseudo-randomized numbers and the data and writing the parity check codes and the data to the memory device when a write operation is performed;
• and
• recovering at least one of the data stored in the memory device using the one or more parity check codes when a read operation is performed and the at least one of the data stored in the memory device is incorrect,
• wherein
• the parity check codes are generated by multiplying the pseudo-randomized numbers and the data and performing a bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data,
• the randomizer seed is selected based on the data and the pseudo-randomized numbers, or
• the randomizer includes a linear feedback shift register (LFSR), the LFSR is specified by a primitive polynomial, the LSFR includes a first number of cascaded shift registers, the data include a second number of pages, the one or more parity check codes include a third number of parity check codes, and two to a power of the first number is greater than multiplication of the second number minus one and the third number minus one.

A memory controller, comprising:

• a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule;
• and
• a codec coupled to the randomizer, the codec configured to generate one or more parity check codes according to the pseudo-randomized numbers and data to be stored in a memory device, the parity check codes to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect,
• wherein
• the codec is configured to generate the panty check codes by multiplying the pseudo-randomized numbers and the data and performing a bit-wise logic operation of multiplications of the pseudo-randomized numbers and the data,
• the randomizer seed is selected based on the data and the pseudo-randomized numbers, or
• the randomizer includes a linear feedback shift register (LFSR), the LFSR is specified by a primitive polynomial and includes a first number of cascaded shift registers, the data include a second number of pages, the one or more parity check codes include a third number of parity check codes, and two to a power of the first number is greater than multiplication of the second number minus one and the third number minus one.