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US 12,602,181 B2Granted
Memory training for power state changes
AssigneeAdvanced Micro Devices, Inc.
InventorsXianglong Du, Kai-Chieh Chan, Haibin Niu
Life of this patent
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Abstract
A data processor includes a memory controller and a physical interface circuit coupled to the memory controller. In response to a system startup, the memory controller controls the physical interface circuit to selectively train a memory based on whether a first memory clock frequency of a plurality of power states equals any other memory clock frequency of the plurality of power states.
Claims20
A data processor, comprising:
- a memory controller;
- and
- a physical interface circuit coupled to the memory controller,
- wherein in response to a system startup, the memory controller controls the physical interface circuit to selectively train a memory at each of a plurality of power states, wherein the memory controller trains the memory at a first power state of the plurality of power states if a memory clock frequency of the first power state of the plurality of power states does not equal the memory clock frequency of any previously trained power state of the plurality of power states, and bypasses training of the memory at the first power state of the plurality of power states if the memory clock frequency of the first power state of the plurality of power states equals the memory clock frequency of at least one previously trained power state of the plurality of power states.
1 more element
A data processing system, comprising:
- a data processor;
- and
- a memory having a plurality of mode registers for storing a configuration state,
- wherein in response to a system startup, the data processor selectively trains the memory at each of a plurality of power states, wherein the data processor trains the memory at a first power state of the plurality of power states if a memory clock frequency of the first power state of the plurality of power states does not equal the memory clock frequency of any previously trained power state of the plurality of power states, and bypasses training of the memory at the first power state of the plurality of power states if the memory clock frequency of the first power state of the plurality of power states equals the memory clock frequency of at least one previously trained power state of the plurality of power states.
1 more element
A method for use in a data processing system, comprising:
- for each of a plurality of power states including a memory clock frequency:
- if the memory clock frequency of a given power state is different from the memory clock frequency of each previously trained power state, training a memory at the memory clock frequency of the given power state and storing training values in shadow registers;
- and
- if the memory clock frequency of the given power state is the same as the memory clock frequency of any previously trained power state, bypassing the training and copying values of a previously trained power state having the same memory clock frequency in the shadow registers for the given power state.
1 more element
Dependencies are inferred from the claim text.