Charge domain compute-in-DRAM for binary neural network

A method for computing in-dynamic random access memory (DRAM) computing, comprising:

• loading a first group of cells of the DRAM with input parameters for computing in-memory in the DRAM;
• loading a second group of cells of the DRAM with inverted input parameters that are each complementary to corresponding input parameters;
• loading an offset group of cells of the DRAM with an indication of an offset voltage;
• performing an operation of weights with corresponding stored input parameters or stored inverted input parameters;
• activating a column of the first group and the second group to perform an accumulation of the operations of weights for cells in the column to store a sum;
• generating an offset voltage in the column using the indication;
• generating an output based on the sum and the offset voltage and storing the output in an output group of cells of the DRAM as a result for in-memory computation performed in the DRAM;
• selecting a word line of the first group based on a first value of a first weight of the weights;
• and
• selecting a word line of the second group based on a second value of a second weight of the weights, wherein the first value and second value are logic complements.

A method for computing in-dynamic random access memory (DRAM) computing, comprising:

• loading a first group of bits in a first array core of the DRAM with input parameters;
• loading a second group of bits in a second array core of the DRAM with inverted input parameters that are complementary to respective input parameters;
• loading an offset group of bits of the DRAM with an indication of an offset voltage;
• multiplying weights with corresponding stored input parameters or inverted input parameters in a charge domain by selecting the first group when the weights have a first value and by selecting the second group when the weights have a second value;
• activating a column including the first group and the second group to perform an accumulation of operations of weights for cells in the column in the charge domain to store a sum on a first digit line of the column;
• generating an offset voltage in the column using the indication by putting an amount of charge on a second digit line, wherein the amount of charge is based at least in part on the indication, wherein each of a plurality of sense amplifiers, as part of the offset voltage generation is configured to:
• equalize respective first digit lines and respective second digit lines by disabling pre-charge and enabling equalization signals for the respective first digit lines and the respective second digit lines;
• disable equalization for the respective second digit lines after accumulation;
• pre-charge the respective digit lines after equalization is disabled;
• and
• change charge on the respective digit lines by a number of pulses and values indicated by respective indications;
• generating an output based on a comparison in the charge domain of the sum on the first digit line and the offset voltage on the second digit line by activating a sense amplifier of the plurality of sense amplifiers to perform the comparison;
• and
• storing the output in an output group of bits of the DRAM via the sense amplifier as a result for in-memory computation performed in the DRAM.