System-on-chip for controlling memory devices and its data training method

A data training method for a memory device, the method comprising:

• sequentially transmitting a plurality of write commands to the memory device according to a specified time interval;
• sequentially transmitting a plurality of pieces of first data with a plurality of different delay times to the memory device through a memory interface based on a pre-stored first edge code in response to each of the plurality of write commands;
• continuously transmitting, to the memory device, a plurality of read commands for reading the plurality of pieces of first data stored in the memory device from the memory device;
• and
• obtaining a first delay value based on a data pattern of pieces of first reception data read from the memory device, wherein first delay value includes an extent to which the plurality of pieces of first data are delayed.

A memory system comprising:

• a memory device;
• and
• a SoC configured to control a memory operation of the memory device,
• wherein the SoC is configured to:
• sequentially transmit a plurality of pieces of first data with a plurality of different delay times to the memory device based on a pre-stored first edge code;
• continuously transmit, to the memory device, a plurality of read commands for reading the plurality of pieces of first data stored in the memory device from the memory device;
• and
• obtain a first delay value based on a data pattern of each piece of a plurality of pieces of first reception data read from the memory device, wherein the plurality of pieces of first data are delayed in the memory device by the first delay value.