Power-on operation execution method and apparatus

A power-on operation execution apparatus, comprising:

• a memory operable to store computer-readable instructions;
• and
• a processor circuitry operable to read the computer-readable instructions, the processor circuitry when executing the computer-readable instructions is configured to:
• start a processor of a chip in response to the chip being connected to a host and a frequency of a first clock signal of the chip being switched to a stable state, wherein the chip comprises a clock gating, a clock phase locked loop, and a controller and physical layer;
• control the first clock signal to enter the clock phase locked loop via the clock gating;
• receive a reset signal transmitted from the host, the reset signal being transmitted in response to a frequency of a second clock signal generated on the host being switched to a stable state;
• execute a power-on operation in response to the reset signal,
• a time point at which the frequency of the first clock signal is switched to the stable state being earlier than a time point at which the frequency of the second clock signal is switched to the stable state;
• initialize the controller and physical layer with the processor;
• in response to the initialization of the controller and physical layer being completed,
• turn off the clock gating to stop the first clock signal from entering the clock phase locked loop;
• switch the first clock signal reaching the clock gating to the second clock signal in response to a duration after stopping the first clock signal from entering the clock phase locked loop reaching a first duration;
• and
• turn on the clock gating to enable the second clock signal to enter the clock phase locked loop in response to a duration after switching the first clock signal reaching the clock gating to the second clock signal reaching a second duration.