Register clock driver, operating method of register clock driver, and memory module including register clock driver and plurality of memory devices

An operating method of a register clock driver which includes an operating circuit and a training circuit, the training circuit including a pattern generating circuit, the method comprising:

• generating, by the pattern generating circuit of the training circuit, a pattern in an initialization operation to be used in a first training operation and a second training operation;
• performing, by the training circuit, the first training operation, in which one of a plurality of reference clock signals is selected as a first training clock signal for sampling output signals output from the operating circuit, in the initialization operation;
• performing, by the training circuit, the second training operation, in which a second training clock signal for sampling the output signals is selected through phase interpolation using the first training clock signal, in the initialization operation, wherein a phase interpolator of the training circuit generates an interpolation clock signal through the phase interpolation using a sampling clock signal;
• and
• sampling, by the training circuit using the interpolation clock signal, the output signals output from the operating circuit in a normal operation such that command address signals are output to external memory devices.

A memory module comprising:

• a plurality of memory devices each including a memory cell array;
• and
• a register clock driver connected with the plurality of memory devices,
• wherein the register clock driver includes:
• an operating circuit configured to buffer a command and an address received from an external memory controller;
• and
• a training circuit configured to perform a first training operation and a second training operation in an initialization operation,
• wherein, in the first training operation, one of a plurality of reference clock signals is selected as a first training clock signal for sampling output signals output from the operating circuit,
• wherein, in the second training operation, a second training clock signal for sampling the output signals is selected through phase adjustment based on the first training clock signal,
• wherein, in a normal operation, the training circuit is configured to sample the output signals based on the second training clock signal and to output command address signals to the plurality of memory devices, and
• wherein the training circuit further includes;
• a control logic circuit including a pattern generating circuit configured to generate a pattern to be used in the first training operation and the second training operation;
• a phase interpolator configured to generate an interpolation clock signal through phase interpolation based on a sampling clock signal;
• and
• an output circuit configured to sample, based on the interpolation clock signal, the output signals output from the operating circuit and to output the command address signals to the plurality of memory devices.