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US 12,599,016 B2Granted
Flip chip package
AssigneeDell Products L.P.
InventorsQinghong He, Isaac Qin Wang
Life of this patent
Estimating the term…
Abstract
In one or more embodiments, a chip may be formed with a first set of contacts on a first surface layer and a second set of contacts on a second surface layer opposite the first surface layer. The first set of contacts may be communication (IO) contacts and the second set of contacts may be power contacts, including ball grid array (BGA) balls and capacitors. A PCB may be configured with a chip receiving area capable of receiving the second set of contacts for various chips.
Claims20
A chip package, comprising:
- a substrate, comprising:
- a first via;
- a second via;
- a third via;
- a fourth via;
- a first trace connected between the first via and the second via;
- a second trace connected between the third via and the fourth via;
- a plurality of layers, including:
- a first surface layer of the plurality of layers comprises a first set of contacts, wherein each contact in the first set of contacts is a first contact type, a particular first contact of the first set of contacts connected to the first via;
- and
- a second surface layer of the plurality of layers opposite the first surface layer comprises a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via;
- and
- a silicon die mounted to the first surface layer;
- a first power contact positioned between the silicon die and the first surface layer, and in contact with the second via;
- a second power contact positioned between the silicon die and the first surface layer, and in contact with the third via;
- wherein the particular first contact at the first surface layer is connected to the first power contact through the first via, the first trace and the second via,
- wherein the particular second contact at the second surface layer is connected to the second power contact through the fourth via, the second trace, and the third via.
14 more elements
A system comprising:
- a printed circuit board (PCB) with a mainboard connector;
- a chip package comprising:
- a substrate, comprising:
- a first via;
- a second via;
- a third via;
- a fourth via;
- a first trace connected between the first via and the second via;
- a second trace connected between the third via and the fourth via;
- a plurality of layers, including:
- a first surface layer of the plurality of layers comprises a first set of contacts, wherein each contact in the first set of contacts is a first contact type, a particular first contact of the first set of contacts connected to the first via;
- and
- a second surface layer of the plurality of layers opposite the first surface layer comprises a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via;
- and
- a silicon die mounted to the first surface layer;
- a first power contact positioned between the silicon die and the first surface layer, and in contact with the second via;
- a second power contact positioned between the silicon die and the first surface layer, and in contact with the third via;
- wherein the particular first contact at the first surface layer is ultimately connected to the first power contact through the first via, the first trace and the second via,
- wherein the particular second contact at the second surface layer is ultimately connected to the second power contact through the fourth via, the second trace, and the third via,
- a connector coupling the first set of contacts to the mainboard connector.
17 more elements
A method of connecting a chip package to a printed circuit board (PCB), the method comprising:
- forming a substrate, comprising:
- forming a first via, a second via, a third via, and a fourth via;
- forming a first trace connected between the first via and the second via;
- forming a second trace connected between the third via and the fourth via;
- forming a first surface layer of the plurality of layers with a first set of contacts, wherein each contact in the first set of contacts is a first contact type a particular first contact of the first set of contacts connected to the first via;
- and
- forming a second surface layer of the plurality of layers opposite the first surface layer with a second set of contacts, wherein each contact in the second set of contacts is a second contact type that is different than the first contact type, a particular second contact of the second set of contacts connected to the fourth via;
- mounting a silicon die to the first surface layer,
- wherein a first power contact is positioned between the silicon die and the first surface layer, and in contact with the second via;
- wherein a second power contact is positioned between the silicon die and the first surface layer, and in contact with the third via;
- mounting the substrate in a chip receiving area on a PCB, wherein the second set of contacts are connected to chip connection points;
- contacting a first end of a connector to the first set of contacts;
- and
- contacting a second end of the connector to a mainboard connector on the PCB,
- wherein the particular first contact at the first surface layer is ultimately connected to the first power contact through the first via, the first trace and the second via,
- wherein the particular second contact at the second surface layer is ultimately connected to the second power contact through the fourth via, the second trace, and the third via.
13 more elements
Dependencies are inferred from the claim text.