Gate-all-around device with protective dielectric layer and method of forming the same

A semiconductor structure comprising:

• a material layer stack disposed over a semiconductor protrusion, wherein the semiconductor protrusion is disposed over and abuts a substrate, the material layer stack includes a dielectric layer disposed over a semiconductor layer, and the semiconductor layer is disposed over the semiconductor protrusion;
• an isolation structure disposed over and abutting the substrate, wherein the isolation structure is disposed along and abuts sidewalls of the semiconductor protrusion;
• and
• a gate stack having a first portion disposed on the isolation structure and a second portion disposed on the material layer stack and the semiconductor protrusion, wherein:
• the gate stack includes a gate dielectric and a gate electrode,
• the gate stack abuts and wraps the dielectric layer, abuts and surrounds the semiconductor layer, and abuts the isolation structure,
• the second portion is disposed between inner spacers along a widthwise direction of the gate stack, and
• the first portion is disposed between gate spacers along the widthwise direction of the gate stack.

A device comprising:

• a first source/drain and a second source/drain disposed over a substrate;
• a channel layer disposed over the substrate, wherein the channel layer extends along from the first source/drain to the second source/drain;
• a gate stack that is disposed on a top, a bottom, and a sidewall of the channel layer, wherein that gate stack includes a gate dielectric and a gate electrode, the gate stack includes a first gate stack portion and a second gate stack portion, the first gate stack portion extends along a gate height direction from a bottom of a gate hard mask to the top of the channel layer, the second gate stack portion extends along the gate height direction from the bottom of the channel layer towards the substrate, the first gate stack portion abuts the bottom of the gate hard mask and the top of the channel layer, and the second gate stack portion abuts the bottom of the channel layer;
• first dielectric spacers disposed along sidewalls of the first gate stack portion, wherein the first dielectric spacers extend along the gate height direction from the gate hard mask to the top of the channel layer, and further wherein the first dielectric spacers abut the gate hard mask, the top of the channel layer, the first source/drain, and the second source/drain;
• and
• second dielectric spacers disposed along sidewalls of the second gate stack portion, wherein the second dielectric spacers extend along the gate height direction from the bottom of the channel layer towards the substrate, and further wherein the second dielectric spacers abut the bottom of the channel layer, the first source/drain, and the second source/drain.