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US 12,598,741 B2Granted
Multi-stack bitcell architecture
AssigneeArm Limited
InventorsYannick Marc Nevers, Valerio Lanieri, Amit Chhabra
Life of this patent
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Abstract
Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.
Claims20
A device comprising:
- a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a wordline is shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline, wherein a global wordline is coupled to the wordline such that the global wordline is shared across the transistors.
A device comprising:
- a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a bitline is shared across the transistors of the multi-stack of transistors with each transistor coupled to a different wordline.
A device comprising:
- a memory architecture having a multi-stack of transistors arranged in a multi-bitcell stack configuration, and wherein a first wordline is shared across a first set of transistors of the multi-stack of transistors with each transistor in the first set of transistors coupled to a first set of shared bitlines, and wherein a second wordline is shared across a second set of transistors of the multi-stack of transistors with each transistor in the second set of transistors coupled to a second set of shared bitlines.
Dependencies are inferred from the claim text.