Resettable level shifting latch
AssigneeQUALCOMM Incorporated
InventorsPeter Normand Labrecque, Sayan Ganguly, Samer Ghanem
Life of this patent
Estimating the term…
Abstract
An apparatus, including: a level shifter configured to: receive an input data signal in a first voltage domain; receive a reset signal in a second voltage domain; and generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal; and a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.
Claims20
An apparatus, comprising:
- a level shifter configured to:
- receive an input data signal in a first voltage domain;
- receive a reset signal in a second voltage domain;
- and
- generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal;
- and
- a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.
A method, comprising:
- receiving an input data signal in a first voltage domain;
- receiving a reset signal in a second voltage domain;
- generating an intermediate signal in the second voltage domain based on the input data signal and the reset signal;
- and
- latching an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.
Dependencies are inferred from the claim text.