Electrostatic discharge protection device

An electrostatic discharge protection device, comprising:

• a P-type semiconductor substrate;
• a first N-type well region located in the P-type semiconductor substrate;
• a first N-type doped region located in the first N-type well region;
• a first P-type doped region located in the first N-type well region, wherein the first P-type doped region and the first N-type doped region are arranged side-by-side and spaced apart from each other;
• a second N-type well region located in the P-type semiconductor substrate, wherein the first N-type well region and the second N-type well region are arranged side-by-side and spaced apart from each other;
• a second N-type doped region located in the second N-type well region;
• a second P-type doped region located in and in contact with the second N-type well region;
• a third P-type doped region located in and in contact with the second N-type well region, wherein the second N-type doped region, the second P-type doped region and the third P-type doped region are arranged side-by-side and spaced apart from one another;
• a first P-type well region located in the first N-type well region;
• a third N-type doped region located in the first P-type well region;
• a fourth P-type doped region located in the first P-type well region, wherein the third N-type doped region and the fourth P-type doped region are arranged side-by-side and spaced apart from each other;
• a second P-type well region located in the first N-type well region, wherein the first P-type well region and the second P-type well region are arranged side-by-side and spaced apart from each other, and the first P-type well region and the second P-type well region are surrounded by the first N-type well region;
• a fourth N-type doped region located in the second P-type well region;
• a fifth P-type doped region located in the second P-type well region, wherein the fourth N-type doped region and the fifth P-type doped region are arranged side-by-side and spaced apart from each other;
• a third P-type well region located in the second N-type well region;
• a fifth N-type doped region located in the third P-type well region;
• and
• a sixth P-type doped region located in the third P-type well region, wherein the fifth N-type doped region and the sixth P-type doped region are arranged side-by-side and spaced apart from each other;
• wherein the first N-type doped region is directly electrically connected to the fifth P-type doped region,
• wherein the second N-type doped region is directly electrically connected to the sixth P-type doped region,
• wherein the first P-type doped region and the fifth N-type doped region are electrically connected to an input/output terminal,
• wherein the second P-type doped region and the third N-type doped region are electrically connected to a power supply terminal, and
• wherein the third P-type doped region, the fourth N-type doped region and the fourth P-type doped region are electrically connected to a ground terminal.