Memory device
AssigneeEtron Technology, Inc.
InventorsChun Shiah, Tzung-Shen Chen
Life of this patent
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Abstract
A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.
Claims18
A memory device, comprising:
- a latch circuit, comprising a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor;
- a first access transistor, coupled to a first storage node of the latch circuit;
- and
- a second access transistor, coupled to a second storage node of the latch circuit, wherein
- the first access transistor is coupled to a first bit line, the second access transistor is coupled to a second bit line, a gate terminal of the first selection transistor is controlled by a first mask bit line, and a gate terminal of the second selection transistor is controlled by a second mask bit line.
A memory device, comprising:
- a latch circuit, comprising a first inverter with a first pull up transistor, a first pull down transistor and a first selection transistor connected in between, and comprising a second inverter with a second pull up transistor, a second pull down transistor and a second selection transistor connected in between;
- a first access transistor, coupled to a first common source/drain terminal shared by the first selection transistor and one of the first pull up transistor and the first pull down transistor;
- and
- a second access transistor, coupled to a second common source/drain terminal shared by the second selection transistor and one of the second pull up transistor and the second pull down transistor, wherein
- the first access transistor is coupled to a first bit line, the second access transistor is coupled to a second bit line, a gate terminal of the first selection transistor is controlled by a first mask bit line, and a gate terminal of the second selection transistor is controlled by a second mask bit line.
Dependencies are inferred from the claim text.