Distributed hybrid buffer for memory systems

A method implemented using a memory and a memory controller configured to communicate with the memory over two or more memory channels, the memory controller including a buffer having a plurality of buffer locations distributed across the two or more memory channels, the method comprising:

• receiving at the memory controller a first write command for writing current data to a memory location within a memory, wherein the memory includes a plurality of stripes, each of the plurality of stripes includes a plurality of memory blocks and a parity block, and the memory location corresponds to one of the plurality of memory blocks in one of the plurality of stripes;
• determining for the memory location whether to store in the buffer at least one of:
• data for the memory location;
• or
• parity for a stripe containing the memory location;
• reading previous data at the memory location;
• reading a previous parity from the parity block in the stripe containing the memory location when it is determined to store the parity in the buffer, wherein the previous parity depends on the previous data;
• updating parity for the stripe containing the memory location to provide a current parity that depends on the current data instead of the previous data;
• writing the current data using a first memory channel to a first buffer location in the buffer when it is determined to store the data in the buffer;
• and
• writing the current parity using a second memory channel into a second buffer location in the buffer when it is determined to store the parity in the buffer.

A method implemented using a memory and a memory controller configured to communicate with the memory over two or more memory channels, the memory controller including a buffer having a plurality of buffer locations distributed across the two or more memory channels, the method comprising:

• receiving at the memory controller both a first read command for reading current data from a memory location within the memory and a prediction, wherein the memory includes a plurality of stripes, each of the plurality of stripes includes a plurality of memory blocks and a parity block, the memory location corresponds to one of the plurality of memory blocks in one of the plurality of stripes, and the prediction indicates whether the memory controller will receive a write command to write updated data to the memory location or write data to another memory location in the stripe within which the current data is being read;
• reading the current data from the memory location;
• determining, based on the prediction, whether to store in the buffer at least one of:
• the read current data for the memory location;
• or
• parity for a stripe containing the memory location;
• writing the read current data for the memory location in a first buffer location when it is determined to buffer the read current;
• reading the parity for the stripe containing the memory location and writing the parity to a second buffer location when it is determined to buffer the parity for the stripe;
• receiving at the memory controller the write command to write updated data to the first location;
• and
• reading the at least one of the read current data for the memory location from the first buffer location or the parity for the stripe containing the memory location from the second buffer location, updating parity for the stripe containing the second memory location to provide an updated parity that depends on the updated data, writing the updated data to the first buffer location in the buffer when it is determined to store the data in the buffer, and writing the current parity to the second buffer location in the buffer when it is determined to store the parity in the buffer.