US 12,593,512 B2Granted

Electrostatic discharge protection circuit

AssigneeRealtek Semiconductor Corp.

InventorChung-Yu Huang

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Abstract

An electrostatic discharge protection circuit including a first transistor, a second transistor, a trigger circuit, a time constant circuit and a bias circuit. The second transistor is coupled with the first transistor in series between a first power line and a second power line. The trigger circuit is configured to switch off the second transistor in a normal operation period. The time constant circuit is configured to control the trigger circuit to output an ESD voltage to the first and second transistors in an ESD period, in order to conduct the first and second transistors. The bias circuit is coupled with the first power line and the gate of the first transistor, and is configured to charge the gate of the first transistor in the normal operation period, in order to generate a predetermined voltage difference between the first power line and the gate of the first transistor.

Claims20

Dependent claims

An electrostatic discharge (ESD) protection circuit, comprising:

a first transistor;
a second transistor, coupled with the first transistor in series between a first power line and a second power line;
a trigger circuit, configured to switch off the second transistor in a normal operation period;
a time constant circuit, coupled with the trigger circuit, configured to control the trigger circuit to output an ESD voltage to a gate of the first transistor and a gate of the second transistor in an ESD period, in order to conduct the first transistor and the second transistor;
and
a bias circuit, coupled with the first power line and the gate of the first transistor, configured to charge the gate of the first transistor in the normal operation period, in order to generate a predetermined voltage difference between the first power line and the gate of the first transistor, wherein the bias circuit comprises:
a third transistor;
and
a fourth transistor, coupled with the third transistor in series between the first power line and the gate of the first transistor;
wherein a source of the fourth transistor is directly electrically connected to a source of the third transistor.

7 more elements

An electrostatic discharge (ESD) protection circuit, comprising:

a clamping circuit, comprising a first control terminal, a second control terminal, a first voltage input terminal and a second voltage input terminal, wherein the first voltage input terminal and the second voltage input terminal are configured to respectively receive a high operating voltage and a low operating voltage in a normal operation period;
a trigger circuit, configured to output the low operating voltage to the second control terminal in the normal operation period to switch off the clamping circuit;
a time constant circuit, coupled with the trigger circuit, configured to control the trigger circuit to output an ESD voltage to the first control terminal and the second control terminal in an ESD period, in order to conduct the clamping circuit to discharge an ESD current through the clamping circuit;
and
a bias circuit, coupled with the first voltage input terminal and the first control terminal, configured to charge the first control terminal in the normal operation period according to the high operating voltage, in order to generate a predetermined voltage difference between the first voltage input terminal and the first control terminal, wherein the bias circuit comprises:
a third transistor;
and
a fourth transistor, coupled with the third transistor in series;
wherein a source of the fourth transistor is directly electrically connected to a source of the third transistor.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/455,617Filed 24 Aug 2023
Priority: TW 11115033928 Dec 2022
Published: US 2024/0222359 A14 Jul 2024
Granted: 31 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10D 89/60
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated devices comprising arrangements for electrical or thermal…
H10D 89/819
Using FETs as protective elements: bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits
H10D
Inorganic electric semiconductor devices