Control gate structures in three-dimensional memory devices and methods for forming the same

A method for forming a three-dimensional (3D) memory device, comprising:

• disposing an alternating layer stack on a substrate, comprising disposing a plurality of first dielectric layers and a plurality of second dielectric layers in an alternating manner;
• etching the alternating layer stack to form a staircase structure;
• disposing a third dielectric layer on the staircase structure;
• disposing an insulating layer on the third dielectric layer;
• removing, the plurality of second dielectric layers to form a plurality of cavities, and the third dielectric layer to form an additional cavity;
• disposing a gate dielectric layer and one or more conductive layers in each cavity of the plurality of cavities and in the additional cavity;
• removing the one or more conductive layers from the additional cavity and disposing an etch stop layer in the additional cavity;
• forming a plurality of openings through the insulating layer, wherein each opening of the plurality of openings terminates at the etch stop layer;
• etching the etch stop layer through the plurality of openings to expose portions of the one or more conductive layers disposed in the each cavity of the plurality of cavities;
• and
• forming a plurality of contacts on the exposed portions of the one or more conductive layers.