Technique for limiting transmission of partial symbols in repeater device

A repeater device, comprising:

• an input configured to receive incoming packet data, wherein the incoming packet data starts with a sync bit pattern that includes N bits in N unit intervals, respectively, where N is a positive integer;
• an output configured to transmit outgoing packet data in response to the incoming packet data having been received at the input, wherein the outgoing packet data is transmitted from the output with N−k bits in N−k unit intervals, where k={1,2,3}, and wherein the outgoing packet data is bit-wise identical with the incoming packet data except k leading bits of the sync bit pattern are omitted from a start of the outgoing packet data;
• a first path coupled between the input and the output, the first path including:
• a receiver having a receiver input and a receiver output;
• the receiver input coupled to the input;
• a transmitter driver having a transmitter driver input and a transmitter driver output;
• the transmitter driver input coupled to the receiver output;
• and
• a switch having a first switch terminal, a second switch terminal, and a switch control terminal;
• the first switch terminal coupled to the transmitter driver output, and the second switch terminal coupled to the output;
• and
• a second path coupled between the input and the switch control terminal, the second path including a variable delay circuit having a variable delay circuit input and a variable delay circuit output and a fixed delay circuit having an input and an output, the variable delay circuit input coupled to the output of the fixed delay circuit and the variable delay circuit output coupled to the switch control terminal.

A device, comprising:

• an input configured to receive incoming data, wherein the incoming data includes N bits in N unit intervals, respectively, wherein N is a positive integer;
• an output configured to transmit outgoing data after the incoming data has been received at the input;
• a first path extending between the input and the output, the first path comprising a transmitter having a transmitter input coupled to the input, a transmitter output coupled to the output, and a transmitter enable;
• and
• a second path extending between the input and the output and comprising a timing control circuit, the timing control circuit including a variable delay circuit in series with a fixed delay circuit, and the timing control circuit having an input coupled to the input of the device and an output coupled to the transmitter enable,
• wherein the outgoing data from the output of the device has N−k bits in N−k unit intervals, respectively, where k=1,2, or 3, and wherein the outgoing data is bit-wise identical to the incoming data except that a leading bit of the outgoing data corresponds to a k+1th bit of the incoming data and bits following the leading bit of the outgoing data respectively correspond to bits following the k+1th bit of the incoming data.