Memory sub-system for memory cell in-field touch-up

A method, comprising:

• detecting a first charge parameter for:
• a first portion of memory of a memory system;
• and
• a second portion of memory of the memory system;
• subsequent to detecting the first charge parameters for the first and the second portions, after a particular time interval, detecting a second charge parameter for the first and the second portions;
• determining:
• a first charge parameter change per time interval for the first portion of memory based on the first charge parameter of the first portion, the second charge parameter of the first portion, and the particular time interval;
• and
• a second charge parameter change per time interval for the second portion of memory based on the first charge parameter of the second portion, the second charge parameter of the second portion, and the particular time interval;
• performing a touch-up operation on each of the first and the second portions of memory at different time points based on their respective charge parameter change per time intervals;
• performing a copyback read on the first and the second portions of memory in association with the touch-up operation by transferring data to a NAND cache register, wherein the copyback read is performed at the different time points based on the respective charge parameter change per time intervals;
• and
• performing a copyback program of the data included in the copyback read and stored in the NAND cache register to the first and the second portions of memory associated with the touch-up operation, wherein the copyback read and the copyback program are performed in response to a distance between voltage distributions for the first and the second portions of memory being less than a threshold distance.

An apparatus, comprising:

• a memory device comprising a first portion of memory of a plurality of portions of memory and a second portion of memory of the plurality of portions of memory;
• and
• a processing device coupled to the memory device, wherein the processing device is configured to:
• detect a first charge parameter for:
• a first portion of memory of the memory device;
• and
• a second portion of memory of the memory device;
• subsequent to detecting the first charge parameters for the first and the second portions after a particular time interval, detect a second charge parameter for the first and the second portions;
• determine:
• a first charge parameter change per time interval for the first portion of memory based on the first charge parameter of the first portion, the second charge parameter of the first portion, and the particular time interval;
• and
• a second charge parameter change per time interval for the second portion of memory based on the first charge parameter of the second portion, the second charge parameter of the second portion, and the particular time interval;
• determine a touch-up trimset for each of the first and the second portions of memory based on their respective charge parameter changes per time interval;
• apply the determined touch-up trimset to each of the first and the second portions of memory;
• perform a copyback read on the first and the second portions of memory in association with the application of the determined touch-up trimset by transferring data to a NAND cache register, wherein the copyback read is performed at the particular time interval based on the charge parameter change per time intervals;
• and
• perform a copyback program of the data included in the copyback read and stored in the NAND cache register to the first and the second portions of memory associated with the application of the determined touch-up trimset, wherein the copyback read and the copyback program are performed in response to a distance between voltage distributions for the first and the second portions of memory being less than a threshold distance.