Semiconductor structure comprising power deliver network structure

A semiconductor structure, comprising:

• a substrate, comprising an element region and a peripheral region surrounding the element region;
• a semiconductor element, disposed on the substrate in the element region;
• an interconnect structure, disposed in the element region, located above the semiconductor element, and electrically connected to the semiconductor element;
• a first power deliver line, disposed above the interconnect structure and electrically connected to a first power source;
• a second power deliver line, disposed above the interconnect structure and electrically connected to a second power source;
• a first power deliver network structure, disposed between the substrate in the peripheral region and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure;
• and
• a second power deliver network structure, disposed between the substrate in the peripheral region and the second power deliver line, and is connected to the second power deliver line and the lowest circuit layer of the interconnect structure,
• wherein the first power deliver network structure comprises:
• a plurality of first power deliver circuit layers;
• and
• a plurality of first power deliver vias, connected to two adjacent first power deliver circuit layers among the first power deliver circuit layers,
• wherein a lowest first power deliver circuit layer of the first power deliver circuit layers is connected to the lowest circuit layer of the interconnect structure, edges of a rest of the first power deliver circuit layers are spaced apart from the interconnect structure by a first distance, and the first distance is between 1 μm and 10 μm,
• wherein the second power deliver network structure comprises:
• a plurality of second power deliver circuit layers;
• and
• a plurality of second power deliver vias, connected to two adjacent power deliver circuit layers among the second power deliver circuit layers,
• wherein a lowest second power deliver circuit layer of the second power deliver circuit layers is connected to the lowest circuit layer of the interconnect structure, edges of a rest of the second power deliver circuit layers are spaced apart from the interconnect structure by a second distance, and the second distance is between 1 μm and 10 μm.