Semiconductor memory device manufacturing method
AssigneeNanya Technology Corporation
InventorChih-Ching Lin
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device manufacturing method includes the following steps. A bit line structure is formed in a memory array area of a substrate. A gate structure is formed in a periphery area of the substrate. A dielectric layer is formed over the bit line structure and the gate structure. A lower hard mask layer is formed over the dielectric layer. An etch process diagnostic signal layer is formed over the lower hard mask layer. An upper hard mask layer is formed over the etch process diagnostic signal layer. A main etching step is performed to form a first via hole towards the bit line structure and a second via hole towards the gate structure until the upper hard mask layer is removed to expose the etch process diagnostic signal layer.
Claims20
A semiconductor memory device manufacturing method comprising:
- forming a bit line structure in a memory array area of a substrate, wherein the bit line structure comprises a bit line metal and a bit line mask;
- forming a gate structure in a periphery area of the substrate, wherein the gate structure comprises a gate electrode and a gate mask;
- forming a dielectric layer over the bit line structure and the gate structure;
- forming a lower hard mask layer over the dielectric layer;
- forming an etch process diagnostic signal layer over the lower hard mask layer;
- forming an upper hard mask layer over the etch process diagnostic signal layer;
- and
- performing a main etching step to form a first via hole towards the bit line structure and a second via hole towards the gate structure until the upper hard mask layer is removed to expose the etch process diagnostic signal layer.
A semiconductor memory device manufacturing method comprising:
- forming a bit line structure in a memory array area of a substrate, wherein the bit line structure comprises a bit line metal and a bit line mask;
- forming a plurality of gate structures in a periphery area of the substrate, wherein each gate structure comprises a gate electrode and a gate mask;
- forming a dielectric layer over the bit line structure and the gate structures;
- forming a hard mask layer containing an etch process diagnostic signal layer over the dielectric layer;
- and
- performing a main etching step to form a first via hole towards the bit line structure, a second via hole towards one of the gate structures and a third via hole towards an active area of the substrate between immediately-adjacent two of the gate structures until the hard mask layer is partially removed to expose the etch process diagnostic signal layer.
Dependencies are inferred from the claim text.