Integrated circuit device and method for fabricating the same
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University, National Taiwan Normal University
InventorsKuo-Yu Hsiang, Chun-Yu Liao, Jen-Ho Liu, Min-Hung Lee
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Abstract
An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.
Claims20
A method for fabricating an integrated circuit device, comprising:
- depositing a bottom electrode layer over a substrate;
- depositing a dielectric film over the bottom electrode layer;
- depositing an antiferroelectric film over the dielectric film by an atomic layer deposition (ALD) process, wherein the ALD process comprises a plurality of cycles, and each of the cycles comprises at least one hafnium-containing precursor pulse and at least one zirconium-containing precursor pulse, wherein a number of the at least one zirconium containing precursor pulse is greater than a number of the at least one hafnium-containing precursor pulse;
- and
- depositing a top electrode layer over the antiferroelectric film.
A method for fabricating an integrated circuit device, comprising:
- forming a bottom electrode over a substrate;
- forming a dielectric layer over the bottom electrode;
- forming an antiferroelectric layer over the dielectric layer, wherein the antiferroelectric layer comprises hafnium zirconium oxide, and a ratio of a zirconium content to a sum of the zirconium content and a hafnium content in the hafnium zirconium oxide is greater than 50% and less than 100%;
- and
- forming a top electrode over the antiferroelectric layer, wherein the bottom electrode, the dielectric layer, the antiferroelectric layer, and the top electrode collectively form a memory device.
A method for fabricating an integrated circuit device, comprising:
- forming an interconnect layer over a substrate, wherein the interconnect layer comprises a conductive feature;
- and
- forming a memory device over the conductive feature of the interconnect layer, wherein the memory device comprises:
- a bottom electrode;
- a dielectric layer over the bottom electrode;
- an antiferroelectric layer over the dielectric layer, wherein the antiferroelectric layer has a thickness greater than a thickness of the dielectric layer, wherein a fraction of a tetragonal phase in the antiferroelectric layer is in a range from about 20% to about 100%;
- and
- a top electrode over the antiferroelectric layer.
Dependencies are inferred from the claim text.