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US 12,588,210 B2Granted
Semiconductor memory device
AssigneeKioxia Corporation
InventorHiroshi Kanno
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. A first memory pillar extends through the first wiring layer. A second memory pillar extends through the second wiring layer. A member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.
Claims20
A semiconductor memory device, comprising:
- a first semiconductor layer;
- a first wiring layer above the first semiconductor layer in a first direction;
- a second wiring layer above the first semiconductor layer in the first direction and spaced from the first wiring layer in a second direction intersecting the first direction;
- a first memory pillar extending in the first direction through the first wiring layer and having a lower end connected to the first semiconductor layer;
- a second memory pillar extending in the first direction through the second wiring layer and having a lower end connected to the first semiconductor layer;
- and
- a first member above the first semiconductor layer in the first direction, between the first and second wiring layers in the second direction, and extending in a third direction orthogonal to the first and second direction, wherein
- the first member includes:
- a first conductor extending in the first direction and contacting the first semiconductor layer,
- a first insulator between the first wiring layer and the first conductor in the second direction and between the second wiring layer and the first conductor in the second direction, and
- a plurality of second insulators arranged along the third direction and between the first conductor and the first semiconductor layer in the first direction.
8 more elements
A semiconductor memory device, comprising:
- a first semiconductor layer;
- a first wiring layer above the first semiconductor layer in a first direction;
- a second wiring layer above the first semiconductor layer in the first direction and spaced from the first wiring layer in a second direction intersecting the first direction;
- a first memory pillar extending in the first direction through the first wiring layer and having a lower end connected to the first semiconductor layer;
- a second memory pillar extending in the third direction through the second wiring layer and having a lower end connected to the first semiconductor layer;
- and
- a first member extending in the first direction and being between the first wiring layer and the second wiring layer in the second direction and extending lengthwise in a third direction orthogonal to the first and second directions, wherein
- the first member includes:
- a first conductor extending in the first direction and contacting the first semiconductor layer,
- a first insulator between the first wiring layer and the first conductor in the second direction and between the second wiring layer and the first conductor in the second direction,
- a plurality of first protruding portions spaced apart from each other in the third direction, the first protruding portions being between the first wiring layer and the first insulator in the second direction, and
- a plurality of second protruding portions spaced apart from each other in the third direction and being between the second wiring layer and the first insulator in the second direction.
9 more elements
A semiconductor memory device, comprising:
- a first semiconductor layer;
- a plurality of wiring layers above the first semiconductor layer in a first direction, the wiring layers separated from each other in the first direction;
- a first slit member extending through the plurality of wiring layers in the first direction;
- a first memory pillar extending in the first direction through the plurality of wiring layers and having a lower end connected to the first semiconductor layer;
- and
- a second memory pillar extending in the first direction through the plurality of wiring layers and having a lower end connected to the first semiconductor layer, the first slit member being between the first and second memory pillars in a second direction intersecting the first direction, wherein
- the first slit member includes:
- a first conductor extending in the first direction and contacting the first semiconductor layer,
- a first insulator sidewall portion between the first memory pillar and the first conductor in the second direction,
- a second insulator sidewall portion between the second memory pillar and the first conductor in the second direction, and
- a plurality of lower insulators arranged along a third direction orthogonal to the first and second direction and between the first conductor and the first semiconductor layer in the first direction.
8 more elements
Dependencies are inferred from the claim text.