US 12,588,203 B2Granted

Semiconductor memory device with decreased parasitic capacitance

AssigneeSK hynix Inc.

InventorsWon Geun Choi, Mi Seong Park, Jung Shik Jang

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Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a gate stacked structure including conductive layers, each of the conductive layers extending in a first direction and a second direction and including a top surface facing a third direction, wherein the conductive layers are stacked to be spaced apart from each other in the third direction. Also, the semiconductor memory device includes a first channel structure and a second channel structure extending in the third direction to pass through the gate stacked structure and spaced apart from each other in the second direction, a first insulating layer disposed over the gate stacked structure, an etch stop layer disposed over the first insulating layer and including a trench, an insulating material in the trench, and a bit line contact passing through the insulating material.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a gate stacked structure including conductive layers, each of the conductive layers extending in a first direction and a second direction and including a top surface facing a third direction, wherein the conductive layers are stacked to be spaced apart from each other in the third direction;
a first channel structure and a second channel structure extending in the third direction to pass through the gate stacked structure and spaced apart from each other in the second direction;
a first insulating layer disposed over the gate stacked structure;
an etch stop layer disposed over the first insulating layer and including a trench, the trench extending in a diagonal direction between the first direction and the second direction;
a second insulating layer including a horizontal portion and a protrusion, the horizontal portion located over the etch stop layer and the protrusion extending from the horizontal portion and into the trench;
a first bit line disposed in the second insulating layer and extending in the second direction to overlap with the first channel structure and the second channel structure;
and
a first bit line contact extending from the first bit line to pass through the first insulating layer in a part where the first bit line overlaps with the trench.

5 more elements

A semiconductor memory device, comprising:

a gate stacked structure including conductive layers, each of the conductive layers extending in a first direction and a second direction and including a top surface facing a third direction, wherein the conductive layers are stacked to be spaced apart from each other in the third direction;
a first channel structure and a second channel structure extending in the third direction to pass through the gate stacked structure and spaced apart from each other in the second direction;
a first insulating layer disposed over the gate stacked structure;
an etch stop layer disposed over the first insulating layer;
a first insulating line and a second insulating line passing through the etch stop layer and the first insulating layer, extending in the second direction to overlap with the first channel structure and the second channel structure, and spaced apart from each other in the first direction;
a first bit line contact passing through the first insulating line and the first insulating layer in a part where the first insulating line overlaps with the first channel structure;
and
a second bit line contact passing through the second insulating line and the first insulating layer in a part where the second insulating line overlaps with the second channel structure.

5 more elements

Dependencies are inferred from the claim text.