Memory device with increased density and method of fabricating the same

A method for manufacturing a memory device, comprising:

• forming at least three source lines over a substrate;
• forming a stack structure over the at least three source lines, where the stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately each other;
• forming a hole in the stack structure;
• forming a charge storage structure on sidewalls of the hole;
• forming a semiconducting layer in the hole;
• patterning the semiconducting layer to form at least three channel pillars within the charge storage structure, wherein the at least three channel pillars connected to the at least three source lines;
• forming an insulating pillar in a remaining space of the hole;
• and
• forming at least three bit lines over the gate stack structure, wherein the at least three bit lines are electrically connected to the at least three channel pillars.

A method for manufacturing a memory device, comprising:

• forming at least three source lines over a substrate;
• forming a stack structure above the at least three source lines, where the stack structure includes a plurality of first material layers and a plurality of second material layers stacked alternately;
• forming a hole in the stack structure;
• forming a semiconducting layer in the hole;
• forming a filling pillar in the semiconducting layer;
• removing the plurality of second material layers to form a plurality of horizontal openings;
• forming a plurality of charge storage structures and a plurality of gate layers in the plurality of horizontal openings, so as to form a gate stack structure including the gate layers and the first material layers;
• patterning the semiconducting layer in the hole to form at least three channel pillars, wherein the at least three channel pillars are electrically isolated from one another, and the charge storage structure are disposed within each of the plurality of gate layers surrounding the at least three channel pillars;
• forming an insulating pillar in a remaining space of the hole;
• and
• forming at least three bit lines over the gate stack structure, wherein the at least three bit lines are electrically connected to the at least three channel pillars,
• wherein the at least three bit lines extending in a first direction, and the at least three source lines extending in a second direction, and an included angle between the first direction and the second direction is an acute angle.