Multi-port SRAM cell with metal interconnect structures

An integrated circuit structure, comprising:

• a device layer including a first gate structure of a first pass-gate transistor, a second gate structure shared by a first pull-down transistor and a first pull-up transistor, a third gate structure shared by a second pull-down transistor and a second pull-up transistor, and a fourth gate structure of a second pass-gate transistor, each of the gate structures extending lengthwise in a first direction;
• and
• a metal layer suspended above the device layer, the metal layer including first, second, third, fourth, fifth, and sixth metal tracks arranged in order from first to sixth along the first direction and each extending lengthwise in a second direction perpendicular to the first direction,
• wherein the third metal track includes a metal line crossing over the third gate structure, and one of the fourth metal track or the fifth metal track includes a metal line crossing over the second gate structure.

A memory array, comprising:

• a first memory cell having at least a first transistor;
• a second memory cell having at least a second transistor, the second memory cell abutting the first memory cell, wherein the first and second transistors share a gate structure that extends across a boundary line between the first and second memory cells;
• a gate contact disposed on the gate structure;
• and
• a metal track suspended above the boundary line, wherein the metal track includes a first pad coupled to a power supply of the first and second memory cells and a second pad in physical contact with the gate contact.