Ramp signal generator and image sensor and electronic device including the same

An image sensor comprising:

• a pixel array including a plurality of pixels;
• a ramp signal generation circuit configured to generate a ramp signal of which a level decreases at a constant slope;
• and
• an analog-to-digital conversion circuit configured to convert a pixel signal provided from the pixel array into a pixel value based on the ramp signal,
• wherein the ramp signal generation circuit includes:
• a load resistor connected between a ground and an output node to which the ramp signal is output, and
• a plurality of current cells, each providing a cell current to the load resistor during a reset period and providing the cell current to the ground during a set period, and
• wherein each of the plurality of current cells includes:
• a first transistor connected between a switching node and the output node, the cell current flowing to the load resistor through the first transistor,
• a second transistor connected between the switching node and the ground, the cell current flowing to the ground through the second transistor, and
• a negative feedback circuit that controls a gate terminal of the first transistor based on a voltage of the switching node so that the first transistor operates in a saturation region.

An electronic device comprising:

• a ramp signal generator that includes a plurality of current cells and a load resistor, the ramp signal generator being configured to control the plurality of current cells to reduce an amount of current flowing through the load resistor and to generate a ramp signal of which a level increases or decreases at a certain slope;
• and
• a main circuit configured to perform at least one predefined function by detecting data based on the ramp signal,
• wherein each of the plurality of current cells includes:
• a first transistor connected between a switching node and an output node, a cell current flowing to the load resistor through the first transistor during a reset period,
• a second transistor connected between the switching node and a ground, the cell current flowing to the ground through the second transistor during a set period, and
• a negative feedback circuit that controls a gate terminal of the first transistor based on a voltage of the switching node so that the first transistor operates in a saturation region.