Output buffer that can prevent drain-source voltage of transistor from briefly exceeding nominal voltage

An output buffer, comprising:

• a first P-type transistor, coupled to a supply voltage;
• a second P-type transistor, coupled between the first P-type transistor and a pad, wherein the first P-type transistor and the second P-type transistor selectively connect the supply voltage and the pad, and the pad is arranged to output an output signal of the output buffer;
• a first N-type transistor, coupled to a grounding voltage;
• a second N-type transistor, coupled between the first N-type transistor and the pad, wherein the first N-type transistor and the second N-type transistor selectively connect the grounding voltage and the pad;
• a control circuit, arranged to generate two first gate control signals according to a control signal, in order to control the first P-type transistor and the first N-type transistor;
• and
• a tracking circuit, coupled to the pad, and arranged to generate a second gate control signal according to the output signal, in order to control the second P-type transistor or the second N-type transistor;
• wherein when the control circuit generates the two first gate control signals according to the control signal for turning off the first P-type transistor and turning on the first N-type transistor, the tracking circuit generates the second gate control signal according to the output signal for turning on the second N-type transistor.