Circuitry arrangement in a floorplan of a memory device

An apparatus, comprising:

• a memory device including a plurality of planes, each plane including a plurality of memory blocks with memory cells;
• the memory device including a CMOS layer that underlies or overlies the memory blocks;
• in the CMOS layer, each of the planes having a sense amplifier area and a non-common peripheral circuitry area;
• the CMOS layer further including at least two common peripheral circuitry areas;
• and
• the planes being oriented such that in the CMOS layer, each of the non-common peripheral circuitry areas is immediately adjacent the at least one of the common peripheral circuitry areas.

A memory device, comprising:

• a plurality of planes, each plane including a plurality of memory blocks with memory cells;
• the memory device including a CMOS layer that underlies or overlies the memory blocks;
• in the CMOS layer, the memory device including a common input/output means for communicating with a controller;
• each of the planes having a peripheral circuitry area and a sense amplifier area, and the planes being arranged such that in the CMOS layer, the peripheral circuitry areas of the plurality of planes are electrically connected with one another and with the input/output means without contacts that run above or below the sense amplifier areas;
• and
• wherein the plurality of planes includes a first set of planes that have major dimensions that extend in a first direction and a second set of planes that include major dimensions that extend in a second direction that is traverse to the first direction and wherein the planes of the first set of planes are larger than the planes of the second set of planes.