Overlay correction for advanced integrated-circuit devices
AssigneeOnto Innovation Inc.
InventorsKeith F. Best, John Chang
Life of this patent
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AssigneeOnto Innovation Inc.
InventorsKeith F. Best, John Chang
Estimating the term…
Various examples described herein include a correction for a layer-to-layer or substrate-to-substrate overlay alignment based upon feedback from critical-dimension (CD) measurements of locations of various features that are to be formed on subsequently formed layers of a substrate with regard to locations of similar features on previously formed layers. The layer-to-layer or substrate-to-substrate overlay-alignment feedback can be enhanced by determining positions of multiple ones of the features on each of the formed layers with respect to the first layer in the stack. Further, the layer-to-layer or substrate-to-substrate overlay-alignment feedback can be enhanced by determining positions of multiple ones of the features on each of the formed layers with respect to the previously formed layer. Overlay-alignment errors may be sent back to a photolithographic exposure tool. An accumulated overlay error can be flagged. Other techniques and methods are also disclosed.
A method for correcting overlay errors in a multi-layer process, the method comprising:
A system to correct overlay errors in a multi-layer process, the system comprising:
Dependencies are inferred from the claim text.