Semiconductor device
AssigneeDenso Corporation
InventorKenji Kouno
Life of this patent
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Abstract
A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.
Claims9
A semiconductor device comprising:
- a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode;
- and
- a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode, wherein
- the JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected, and
- when a drain voltage dependency of a gate voltage of the JFET is referred to as a gate voltage dependency denoted by ΔVgJ, ΔVgJ is within a range equal to or greater than the following equation (1) and equal to or less than the following equation (2):
- ΔVgJ=(Vd×Id−ΔtmJ×Id×dV/dt)/g/(Cgd/Ciss)/(Vd−ΔtmJ×dV/dt) (1)
- ΔVgJ=Vd/g/(Cgd/Ciss)×(dI/dt/dV/dt)−ΔtmJ/g/(Cgd/Ciss)×dI/dt (2),
- where dI/dt denotes a current change rate, dV/dt denotes a voltage change rate, Vd denotes a power supply voltage, Id denotes an operating current, ΔtmJ denotes a delay time of the JFET, Cgd denotes a mirror capacitance of the MOSFET, Ciss denotes an input capacitance of the MOSFET, Vm denotes a gate mirror potential of the MOSFET, Vth denotes a gate threshold of the MOSFET, and g denotes Id/(Vm−Vth).
A semiconductor device comprising:
- a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode;
- and
- a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode, wherein
- the JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected,
- when a mirror capacitance of the MOSFET is denoted by Cgd, an input capacitance of the MOSFET is denoted by Ciss, and a capacitance ratio of the mirror capacitance to the input capacitance is denoted by Cgd/Ciss, Cgd/Ciss is within a range equal to or greater than the following equation (3) and equal to or less than the following equation (4):
- Cgd/Ciss=Id/g/ΔVgJ (3)
- Cgd/Ciss=(Vd/ΔVgJ)×dI/dt/(g×dV/dt)−ΔtmJ/ΔVgJ/(g×dI/dt) (4),
- where ΔVgJ denotes a gate voltage dependency as a drain voltage of a gate voltage of the JFET, dI/dt denotes a current change rate, dV/dt denotes a voltage change rate, Vd denotes a power supply voltage, Id denotes an operating current, ΔtmJ denotes a delay time of the JFET, Vm denotes a gate mirror potential of the MOSFET, Vth denotes a gate threshold of the MOSFET, and g denotes Id/(Vm−Vth).
Dependencies are inferred from the claim text.