High-speed multi-write read only memory array
AssigneeYield Microelectronics Corp.
InventorsYu-Ting Huang, Chi-Pei Wu, Ya-Ting Fan
Life of this patent
Estimating the term…
Abstract
A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.
Claims57
A high-speed multi-write read only memory array comprising:
- a plurality of word lines, arranged in parallel, comprising a first word line;
- a plurality of select lines arranged in parallel, wherein the plurality of select lines perpendicular to the plurality of word lines comprise a first select line and a second select line;
- a plurality of bit lines arranged in parallel, wherein the plurality of bit lines parallel to the plurality of select lines comprise a first bit line, a second bit line, a third bit line, and a fourth bit line, the first select line is arranged between the first bit line and the second bit line, and the second select line is arranged between the third bit line and the fourth bit line;
- and
- a plurality of sub-memory arrays each coupled to one of the plurality of word lines, two of the plurality of select lines, and four of the plurality of bit lines, wherein each of the plurality of sub-memory arrays comprises:
- a first memory cell coupled to the first word line, the first bit line, and the first select line;
- a second memory cell coupled to the first word line, the second bit line, and the first select line;
- a third memory cell coupled to the first word line, the third bit line, and the second select line;
- and
- a fourth memory cell coupled to the first word line, the fourth bit line, and the second select line.
Dependencies are inferred from the claim text.