Divider phase alignment among multiple transmit and receive chains

A device for wireless communication, comprising:

• a processing system that includes processor circuitry and memory circuitry that stores code and is coupled with the processor circuitry, the processing system configured to cause the device to:
• receive a reference signal at a respective input of a plurality of transmitter chains;
• process, by each transmitter chain, the reference signal and a respective local oscillator signal of the receive chain to generate a respective output signal;
• provide the output signals from the transmitter chains to respective inputs of a plurality of receive chains;
• process, by each receive chain, a respective output signal of the received output signals from the transmitter chains to generate a corresponding phase calibration signal;
• determine, for each receive chain, a phase alignment difference for the corresponding phase calibration signal of each receive chain and a reference output of a reference receive chain of the plurality of receive chains, wherein the phase alignment difference is indicative of transmitter chain phase misalignment;
• and
• adjust a phase alignment of a divider of at least one transmitter chain of the plurality of transmitter chains based on the determined phase alignment difference for the at least one transmitter chain.

A base station transceiver system, comprising:

• a first chip including:
• a plurality of first receive chains;
• and
• first synthesizer circuitry configured to provide one or more first local oscillator (LO) signals to the first receive chains;
• a second chip including:
• a plurality of second receive chains;
• and
• second synthesizer circuitry configured to provide one or more second LO signals to the second receive chains;
• one or more oscillators external to the first chip and the second chip and configured to provide an oscillator signal to the first synthesizer circuitry and the second synthesizer circuitry;
• a reference signal generation circuit configured to selectively provide a common input signal to inputs of the first receive chains of the first chip and the second receive chains of the second chip;
• and
• a processor circuit configured to process received signals through the first and second receive chains in response to the common input signal.

A base station transceiver system, comprising:

• a first chip including:
• a plurality of first feedback receive chains and a plurality of first transmit chains;
• and
• first synthesizer circuitry configured to provide one or more first local oscillator (LO) signals to the first feedback receive chains and the first transmit chains;
• a second chip including:
• a plurality of second feedback receive chains and a plurality of second transmit chains;
• and
• second synthesizer circuitry configured to provide one or more second LO signals to the second feedback receive chains and second transmit chains;
• one or more oscillators external to the first chip and the second chip and configured to provide an oscillator signal to the first synthesizer circuitry and the second synthesizer circuitry;
• a reference signal generation circuit configured to selectively provide a common input signal to inputs of the first transmit chains of the first chip and the second transmit chains of the second chip;
• a loopback circuit configured to selectively provide output signals from outputs of the first transmit chains of the first chip and the second transmit chains of the second chip to inputs of the first feedback receive chains of the first chip and the second feedback receive chains of the second chip;
• and
• a processor circuit configured to process received signals through the first and second feedback receive chains in response to the common input signal to the first and second transmit chains.