Programmable clock divider for radio frequency (RF) mixers

A method, comprising:

• receiving an input clock signal at a clock divider;
• generating a first plurality of clock signals with a first clock loop in the clock divider based on the input clock signal with a corresponding first plurality of phases;
• receiving a second clock loop enable signal to enable a second clock loop in the clock divider;
• after receiving the second clock loop enable signal, generating a second plurality of clock signals with the second clock loop based on the input clock signal with a corresponding second plurality of phases;
• and
• synchronizing the second clock loop with the first clock loop after receiving the second clock loop enable signal to obtain a predetermined offset between the corresponding first plurality of phases and the corresponding second plurality of phases, wherein the synchronizing includes retiming the second clock loop enable signal based on the input clock signal.

An apparatus, comprising:

• a clock signal input node;
• a first clock loop circuit coupled to the clock signal input node and configured to output a first plurality of clock signals corresponding to at least two phases based on an input clock signal, wherein the first clock loop circuit comprises:
• a first latch coupled to the clock signal input node, wherein at least one of the first plurality of clock signals is output from the first latch;
• and
• a second latch coupled to the first latch and to the clock signal input node, wherein the second latch comprises a first programmable number of active latches;
• and
• a second clock loop circuit coupled to the clock signal input node and configured to output a second plurality of clock signals corresponding to at least two phases, wherein the second clock loop circuit is configured to be enabled or disabled based on an enable signal;
• and
• a synchronization circuit coupled to the second clock loop circuit and to the first clock loop circuit to initialize the second clock loop circuit with a predetermined phase offset from one of the first plurality of clock signals when the second clock loop circuit is enabled based on a change of the enable signal, wherein the synchronization circuit is configured to retime the enable signal based on the input clock signal coupled to the first clock loop circuit.

A method, comprising:

• receiving, at a clock divider circuit, a configuration signal indicating a divider ratio for a first plurality of clock signals with respect to an input clock signal;
• adjusting, by the clock divider circuit, a first number of active latches in a first programmable latch of the clock divider circuit based on the configuration signal;
• generating, by the clock divider circuit, at least a first clock signal of the first plurality of clock signals from a first main latch coupled to the first programmable latch, wherein the latches of the first main latch are larger latches than latches of the first programmable latch;
• and
• adjusting, by the clock divider circuit, a second number of active latches in a second programmable latch of the clock divider circuit based on the configuration signal.