Method of forming semiconductor device including daisy-chained delay cells

A method of forming a semiconductor device, the method comprising:

• forming active regions, including doping areas of a substrate;
• forming source/drain (S/D) regions, including doping first areas of the active regions that represent first transistor-components with a result that second areas of the active regions between corresponding ones of the first areas are channel regions representing second transistor-components;
• forming gate lines representing third transistor-components over corresponding ones of the channel regions;
• forming metal-to-S/D (MD) contact structures representing fourth transistor-components over corresponding ones of the S/D regions, the MD contact structures defining:
• a first set of the first to fourth transistor-components that lack connections to the first and third transistor-components which otherwise would be indicative of configurations as active transistors such that the first to fourth transistor-components of the first set represent one or more corresponding dummy transistors that define a first dummy group;
• and
• a second set of the first to fourth transistor-components that lack connections to the first and third transistor-components which otherwise would be indicative of configurations as active transistors such that the first to fourth transistor-components of the second set represent one or more corresponding dummy transistors that define a second dummy group;
• and
• forming interconnection structures representing fifth transistor-components over corresponding ones of the gate lines and the MD contact structures, the interconnection structures defining:
• a third set of the first to fifth transistor-components connected as one or more corresponding active transistors that define a first delay cell in which:
• a basic inverter is configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the basic inverter;
• and
• a float-resistant inverter is configured to receive the first inverted signal at the second node and output a second inverted signal at a third node;
• a fourth set of the first to fifth transistor-components connected as one or more corresponding active transistors that define a second delay cell;
• and
• relative to a first direction:
• the first and second dummy groups and the first and second delay cells being in a first row that extends in the first direction, the first row having a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group;
• and
• the first and second delay cells being free from having another dummy group therebetween.