Semiconductor integrated circuit, semiconductor device, and semiconductor memory device

A semiconductor integrated circuit configured to generate an L-bit, wherein L is an integer of 3 or more gray code according to a count value of a first clock signal, the semiconductor integrated circuit comprising:

• a first flip-flop including a clock terminal to which the first clock signal is configured to be input;
• a second flip-flop including a clock terminal to which the first clock signal is configured to be input, a first signal output from a Q terminal of the second flip-flop being input to a D terminal of the first flip-flop;
• an inverter configured to perform an inversion operation on a second signal output from a Q terminal of the first flip-flop, a third signal obtained by inverting the second signal output from the inverter being input to a D terminal of the second flip-flop;
• (L−1) adders, each configured to respectively generate and operate on a different bit of the gray code by performing addition based on a respective bit of an input carry signal;
• a circuit block configured to generate the input carry signal and output a first bit of the input carry signal to a first adder of the (L−1) adders by performing an AND operation of the first signal and the third signal, and output a respective bit of the remaining bit or bits of the input carry signal to each of a second adder to an (L−1)th adder of the (L−1) adders based on the first signal and the second signal;
• a first terminal configured to output the first signal;
• and
• (L−1) second terminals configured to output a set of signals output from the (L−1) adders.