Multiple state programmable memory
AssigneeTexas Instruments Incorporated
InventorsJack Qian, Kemal Tamer San, Guruvayurappan S Mathur
Life of this patent
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Abstract
Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.
Claims18
An integrated circuit comprising:
- a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate, each polycrystalline silicon resistor having a resistor body with a first end and a second end, the first end connected to a current source and the second end connected to a resistance discriminator,
- wherein a first proper subset of the polycrystalline silicon resistors have a first resistance, and a second first proper subset of the polycrystalline silicon resistors have a different second resistance.
An integrated circuit, comprising:
- a memory array over a semiconductor substrate including a plurality of memory storage locations;
- and
- a corresponding polycrystalline silicon resistor in each memory storage location, a first proper subset of the polycrystalline silicon resistors having a resistance in a first resistance range, a second proper subset of the polycrystalline silicon resistors having a resistance in a second resistance range less than the first resistance range and a third proper subset of the polycrystalline silicon resistors having a resistance in a third resistance range less than the second resistance range, the first, second and third resistance ranges being non-overlapping.
A method of forming an integrated circuit, comprising:
- forming a plurality of polycrystalline silicon resistors over a semiconductor substrate;
- passing a non-rupture first current through each resistor of a first proper subset of the polycrystalline silicon resistors thereby decreasing the resistance of the resistors in the first proper subset by a first delta resistance;
- and
- passing a non-rupture second current through each resistor of a second proper subset of the polycrystalline silicon resistors thereby decreasing the resistance of the resistors in the second proper subset by a greater second delta resistance.
Dependencies are inferred from the claim text.