US 12,550,347 B2 · Semiconductor device and semiconductor circuit

Abstract

A semiconductor device according to an embodiment includes a first trench, a first gate electrode in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, a third gate electrode in the third trench, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, and a third electrode pad electrically connected to the third gate electrode, in which a thickness of a conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive semiconductor region opposed to the first gate electrode, and in which the thickness of the conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive type semiconductor region opposed to the second gate electrode.

A semiconductor device comprising:

a semiconductor layer including a first face and a second face opposed to the first face;
a first semiconductor region of a first conductivity type provided in the semiconductor layer;
a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first face;
a third semiconductor region of the first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first face;
a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first face;
a fifth semiconductor region of the second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the third semiconductor region, and having a higher second conductivity type impurity concentration than a second conductivity type impurity concentration of the second semiconductor region;
a sixth semiconductor region of the first conductivity type provided in the semiconductor layer, provided between the third semiconductor region and the first face, and having a higher first conductivity type impurity concentration than a first conductivity type impurity concentration of the third semiconductor region;
a first trench provided in the semiconductor layer on a side of the first face, the first trench extending in a first direction parallel to the first face, and being in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region;
a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, between the first gate electrode and the fourth semiconductor region, between the first gate electrode and the fifth semiconductor region, and between the first gate electrode and the sixth semiconductor region;
a second trench provided in the semiconductor layer on the side of the first face, the second trench extending in the first direction, and being in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region;
a second gate electrode provided in the second trench;
a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, between the second gate electrode and the fourth semiconductor region, between the second gate electrode and the fifth semiconductor region, and between the second gate electrode and the sixth semiconductor region;
at least one third trench provided in the semiconductor layer on the side of the first face, the at least one third trench extending in the first direction, and being in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region;
a third gate electrode provided in the at least one third trench;
a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, between the third gate electrode and the fourth semiconductor region, between the third gate electrode and the fifth semiconductor region, and between the third gate electrode and the sixth semiconductor region;
a first electrode provided on the semiconductor layer on the side of the first face and in contact with the fourth semiconductor region;
a second electrode provided on the semiconductor layer on a side of the second face and in contact with the first semiconductor region;
a first electrode pad provided on the semiconductor layer on the side of the first face and electrically connected to the first gate electrode;
a second electrode pad provided on the semiconductor layer on the side of the first face and electrically connected to the second gate electrode;
and
a third electrode pad provided on the semiconductor layer on the side of the first face and electrically connected to the third gate electrode,
wherein the sixth semiconductor region provided in the first direction of the fourth semiconductor region, and the sixth semiconductor region is in contact with the fourth semiconductor region in the first direction,
wherein in a first cross section perpendicular to the first direction and including the fourth semiconductor region, the fourth semiconductor region is in contact with the first trench, the second trench, and the at least one third trench,
wherein in a second cross section perpendicular to the first direction and including the sixth semiconductor region, the sixth semiconductor region is in contact with the first trench, the second trench, and the at least one third trench,
wherein the third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with the at least one third trench,
wherein the first portion is in contact with the fourth semiconductor region and the fifth semiconductor region in a third direction from the first face toward the second face in the first cross section, and the first portion is in contact with the sixth semiconductor region and the fifth semiconductor region in the third direction in the second cross section,
wherein the second portion is in contact with the fourth semiconductor region and the fifth semiconductor region in the third direction in the first cross section, and the second portion is in contact with the sixth semiconductor region and the fifth semiconductor region in the third direction in the second cross section,
wherein the third portion is in contact with the fourth semiconductor region and the fifth semiconductor region in the third direction in the first cross section, and the third portion is in contact with the sixth semiconductor region and the fifth semiconductor region in the third direction in the second cross section,
wherein a thickness of the third portion provided between the fourth semiconductor region and the fifth semiconductor region in the third direction is smaller than a thickness of the first portion provided between the fourth semiconductor region and the fifth semiconductor region in the third direction, and
wherein the thickness of the third portion provided between the fourth semiconductor region and the fifth semiconductor region in the third direction is smaller than a thickness of the second portion provided between the fourth semiconductor region and the fifth semiconductor region in the third direction.

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Semiconductor device and semiconductor circuit

Life of this patent

Semiconductor device and semiconductor circuit

Life of this patent

Abstract

Claims20