Receiver including a pulse amplitude modulation decoder, and a memory device including the same

A receiver comprising an n-level pulse amplitude modulation (PAM-n) decoder, wherein the PAM-n decoder comprises:

• a comparator receiving first input data, second input data, and a clock signal and outputting first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data;
• a clock delay circuit delaying the clock signal to generate a delayed clock signal;
• and
• a time-windowed least significant bit (LSB) decoder receiving the first comparison data, the second comparison data, and the delayed clock signal,
• wherein the time-windowed LSB decoder performs a decoding when the delayed clock signal is at a first level.

A memory device comprising an interface configured to receive input data based on n-level pulse amplitude modulation (PAM-n), wherein the interface comprises a PAM-n decoder, and

• the PAM-n decoder comprises:
• a comparator that receives first input data, second input data, and a clock signal and outputs first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data;
• a clock delay circuit that delays the clock signal to generate a delayed clock signal;
• and
• a time-windowed least significant bit (LSB) decoder that receives the first comparison data, the second comparison data, and the delayed clock signal,
• wherein the time-windowed LSB decoder performs a decoding when the delayed clock signal is at a first level.