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US 12,541,143 B2Granted
Fully reflective phase-edge mask for EUV lithography
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWen-Hao Cheng
Life of this patent
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Abstract
A EUV lithography mask includes a substrate of a low thermal expansion material, a first reflective multilayer over the substrate, and a patterned reflective multilayer over the first reflective multilayer. The patterned reflective multilayer includes trenches through the patterned reflective multilayer. Each of the first reflective multilayer and the patterned reflective multilayer includes a stack of film pairs.
Claims20
A method, comprising:
- receiving a structure having a substrate of a low thermal expansion material, a first reflective multilayer over the substrate, a silicon carbide layer over the first reflective multilayer, and a second reflective multilayer over and in direct contact with the silicon carbide layer, and a capping layer directly on the second reflective multilayer;
- forming a patterned resist over the second reflective multilayer;
- etching a first portion of the second reflective multilayer through the patterned resist until the silicon carbide layer is exposed, while maintaining a second portion of the second reflective multilayer over the silicon carbide layer, thereby forming a first trench in the second reflective multilayer, a first ridge and a second ridge disposed on each side of the first trench, wherein a first edge of the first ridge and second edge of the second ridge define respective sidewalls of the first trench and correspond to patterns of line/space patterns of one or more target integrated circuit devices, wherein the first ridge includes a first top surface extending from the first edge to a third edge and wherein the second ridge includes a second top surface extending from the second edge to a fourth edge;
- and
- removing the patterned resist;
- wherein after removing the patterned resist, the capping layer extends on an entirety of the first top surface of the first ridge extending from the first edge to the third edge and an entirety of the second top surface of the second ridge extending from the second edge to the fourth edge, wherein an entirety of an upper surface of the capping layer is free from absorption material and forms an uppermost surface of an EUV lithography mask;
- and
- providing a dipole illumination source to create the line/space patterns on a semiconductor substrate, wherein the dipole illumination source is optimized to iso-focal condition of 2-beam interference for the line/space pattern and the dipole illumination source defined by a sigma of partial coherence of approximately 0.8.
5 more elements
A method of EUV lithography, comprising:
- receiving a structure having a substrate of a low thermal expansion material and a first reflective multilayer in direct contact with the substrate, wherein the first reflective multilayer consists of a stack of two alternating films of different materials;
- forming a stop layer across a top surface of the first reflective multilayer, wherein the stop layer is disposed directly touching a first film of the two alternating films;
- forming a second reflective multilayer over the stop layer, wherein the second reflective multilayer consists of a stack of two alternating films of different material forming a patterned resist over the second reflective multilayer;
- forming a protective layer over the second reflective multilayer;
- forming a patterned resist over the protective layer and the second reflective multilayer;
- etching the second reflective multilayer through the patterned resist to form a plurality of trenches of a first depth exposing an upper surface of the stop layer to provide a bottom surface of each trench at the first depth and form ridges of the second reflective multilayer extending between each trench of the plurality of trenches, the ridges each having at least two sidewalls extending from a top surface of the ridge to a top surface of the protective layer, wherein the trenches correspond to a pattern of an integrated circuit device, wherein an entirety of the bottom surface of each of the trenches is the stop layer and wherein the stop layer extends under each of the ridges;
- and
- wherein the pattern of the integrated circuit device is one of a first pattern of a plurality of lines and spaces or a second pattern of a plurality of holes in an array;
- wherein after removing the patterned resist, an entirety of the top surface of each of the ridges has the protective layer extending between the at least two sidewalls of each of the ridges, an entirety of an upper surface of the protective layer being exposed;
- providing a radiation beam to the structure including to the bottom surface of each trench and each of the ridges having the exposed upper surface of the protective layer, wherein the radiation beam is delivered from a source pupil having a sigma of approximately 0.8, and wherein the radiation beam is a dipole illumination source when the pattern is the first pattern and a quadrupole illumination source when the pattern is the second pattern;
- and
- reflecting a first portion of the radiation beam from the ridges and a second portion of the radiation beam from the trenches, wherein the reflected first portion and second portion differ in phase.
9 more elements
Dependencies are inferred from the claim text.