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US 12,537,516 B2Granted
Single pin clock-free retention flip-flop
AssigneeSTMicroelectronics International N.V.
InventorRohit Kumar Gupta
Life of this patent
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Abstract
A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.
Claims20
A method, comprising:
- powering a first latch and a second latch of a retention flip-flop with a primary supply voltage;
- powering a retention latch of the flip-flop with a secondary supply voltage;
- interrupting the primary supply voltage responsive to receiving a retention control signal at the retention flip-flop;
- and
- latching an output data value of the flip-flop with the retention latch responsive to receiving the retention control signal.
2 more elements
An integrated circuit, comprising a retention flip-flop, the retention flip-flop including:
- a first latch configured to receive a primary supply voltage;
- a second latch configured to receive the primary supply voltage;
- a retention latch configured to receive a secondary supply voltage and including a first terminal configured to receive a retention control signal to activate the retention latch;
- and
- a clock generation circuit configured to generate a clock signal and including a second terminal configured to receive the retention control signal.
2 more elements
A method, comprising:
- operating a retention flip-flop in a standard mode including:
- supplying a primary supply voltage to a first latch and a second latch of the retention flip-flop;
- supplying a secondary supply voltage to a retention latch of the retention flip-flop;
- and
- generating a clock signal;
- and
- transitioning the retention flip-flop from the standard mode to a retention mode responsive to receiving a retention control signal, the retention mode including interrupting generation of the clock signal responsive to receiving the retention control signal.
4 more elements
Dependencies are inferred from the claim text.