Differential signaling receiver

A differential signal receiver, comprising:

• a first differential difference amplifier configured to compare a voltage value of an input signal with a first threshold value, and output a first difference signal according to a comparison result of the first differential difference amplifier;
• a second differential difference amplifier configured to compare the voltage value of the input signal with a second threshold value, and output a second difference signal according to a comparison result of the second differential difference amplifier, wherein the second threshold value is an opposite value of the first threshold value;
• a latch coupled to the first differential difference amplifier and the second differential difference amplifier, wherein, the latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal, and in response to the first difference signal and the second difference signal being a logic high level and a logic low level, respectively, the latch is configured to output a first latch signal with the logic low level, and in response to the first difference signal and the second difference signal being the logic low level and the logic high level, respectively, the latch is configured to output the first latch signal with the logic high level;
• and
• a first inverter coupled to the latch, wherein the first inverter is configured to receive the first latch signal and output a first output signal, and the first output signal has a duty cycle being the same as a duty cycle of the input signal.