Latch circuits and methods for operating the same

A circuit, comprising:

• a global input terminal configured to receive an input signal;
• a global output terminal configured to provide an output signal;
• a first sub-latch coupled between the global input terminal and the global output terminal, and comprising a first Dual Interlocked Storage Cell (DICE) component and a second DICE component;
• a second sub-latch coupled between the global input terminal and the global output terminal, and comprising a third DICE component and a fourth DICE component;
• a first buffer coupled between the first sub-latch and the global output terminal;
• and
• a second buffer coupled between the second sub-latch and the global output terminal;
• wherein the first and third DICE components are configured to be in a first operation state, while the second and fourth DICE components are configured to be in a second, different operation state.

A method, comprising:

• providing a loop including at least a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component, wherein the first and second DICE components form a first sub-latch, the third and fourth DICE components form a second sub-latch;
• receiving, by the first sub-latch and the second sub-latch, an input signal;
• providing, by the first sub-latch, an intermediate signal based on the input signal at a first node;
• providing, by the second sub-latch, the intermediate signal based on the input signal at a second node;
• logically inverting, by a first inverter and a second inverter, the intermediate signal;
• providing, at a third node, an output signal.