Sense amplifier based flip-flop

A system, comprising:

• a first sense amplifier having a first data input, a second data input, a clock input, a first output, and a second output, wherein the clock input of the first sense amplifier is configured to receive a first clock signal, the first data input of the first sense amplifier is configured to receive a first data signal, and the second data input of the first sense amplifier is configured to receive a second data signal;
• a second sense amplifier having a first data input, a second data input, a clock input, a first output, and a second output, wherein the clock input of the second sense amplifier is configured to receive a second clock signal, the first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier;
• and
• a set-reset (S-R) latch having a first set input, a second set input, a first reset input, a second reset input, and an output, wherein the first set input is coupled to the first output of the first sense amplifier, the second set input is coupled to the first output of the second sense amplifier, the first reset input is coupled to the second output of the first sense amplifier, and the second reset input is coupled to the second output of the second sense amplifier;
• wherein the first sense amplifier is configured to generate first complementary logic values at the first output of the first sense amplifier and the second output of the first sense amplifier based on the first data signal and the second data signal during a first portion of a cycle of the first clock signal;
• wherein the second sense amplifier is configured to generate second complementary logic values at the first output of the second sense amplifier and the second output of the second sense amplifier based on the first data signal and the second data signal during a second portion of the cycle of the first clock signal;
• and
• wherein the first clock signal is high during the first portion of the cycle of the first clock signal, and the first clock signal is low during the second portion of the cycle of the first clock signal.