Fractional frequency divider
AssigneeTexas Instruments Incorporated
InventorsNarala Reddy, Peeyoosh Mirajkar
Life of this patent
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Abstract
An apparatus includes a counter having a clock input, a count value input, a third input, and an output. A multiplexer has a first input, a second input, a selection input, and an output. A delay circuit has a first input coupled to the clock input of the counter, a second input coupled to the output of the counter, a first output and a second output. The first output is coupled to the first input of the multiplexer, and the second output is coupled to the second input of the multiplexer. A fractional control circuit has a first output coupled to the selection input of the multiplexer and has a second output coupled to the third input of the counter.
Claims20
An apparatus, comprising:
- a counter having a clock input, a count value input, a third input, and an output;
- a multiplexer having a first input, a second input, a selection input, and an output;
- a delay circuit having a first input coupled to the clock input of the counter, a second input coupled to the output of the counter, a first output and a second output, the first output coupled to the first input of the multiplexer, and the second output coupled to the second input of the multiplexer;
- and
- a fractional control circuit having a first output coupled to the selection input of the multiplexer and having a second output coupled to the third input of the counter.
An apparatus, comprising:
- a counter having a clock input, a count value input, an enable offset input, and an output;
- a synchronizer having a first input, a second input, a third input, and an output, the first input coupled to the clock input, and the second input coupled to the output of the counter;
- and
- a fractional control circuit having a fractional control input and an output, the output of the fractional control circuit coupled to the third input of the synchronizer, the fractional control circuit configured to program a delay for the synchronizer based on a signal at the fractional control input and an output clock signal from the apparatus.
An apparatus, comprising:
- a resonator having an output;
- a counter having a clock input coupled to the output of the resonator, a count value input, an enable offset input, and an output;
- a multiplexer having a first input, a second input, a third input, a selection input, and an output;
- a delay circuit having an input coupled to the clock input of the counter and having a first output, a second output, and a third output, the first output coupled to the first input of the multiplexer, the second output coupled to the second input of the multiplexer, and the third output coupled to the third input of the multiplexer;
- and
- a fractional control circuit having a control output coupled to the selection input of the multiplexer and having an enable offset output coupled to the enable offset input of the counter.
Dependencies are inferred from the claim text.