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US 12,525,272 B2Granted
Systems and methods for scan chain interface for non-volatile storage bits
AssigneeEverspin Technologies, Inc.
InventorsSyed M. Alam, Jacob T. Williams
Life of this patent
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Abstract
A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.
Claims9
A scan chain circuitry for a memory device, comprising:
- a first non-volatile storage bit (nvbit) configured to receive a shared control signal;
- a second nvbit configured to receive the shared control signal;
- a first flip-flop connected to the first nvbit;
- and
- a second flip-flop connected to the second nvbit and the first flip-flop,
- wherein the first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and
- wherein the second flip-flop enables loading a second din to the second nvbit based on the clock signal.
4 more elements
Dependencies are inferred from the claim text.