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US 12,524,035 B2Granted
NP5 fractional clock divider
AssigneeQUALCOMM Incorporated
InventorsHarsha Kamath, Neha Agrawal
Life of this patent
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Abstract
An apparatus, including: a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer; and a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction.
Claims24
An apparatus, comprising:
- a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein the clock source comprises a tri-state ring oscillator configured to generate a first set of one or more clock signals, wherein the first and second clock signals are based on the first set of one or more clock signals;
- the apparatus further comprising a duty cycle control circuit configured to generate the first and second clock signals based on the first set of one or more clock signals;
- wherein the first set of one or more clock signals includes third and fourth clock signals, and wherein the duty cycle control circuit comprises:
- a first negative latch including a data input configured to receive the third clock signal, a clock input configured to receive the input clock signal, and a data output configured to generate a fifth clock signal being shifted with respect to the third clock signal by substantially a half cycle of the input clock signal;
- a second negative latch including a data input configured to receive the fourth clock signal, a clock input configured to receive the input clock signal, and a data output configured to generate a sixth clock signal being shifted with respect to the fourth clock signal by substantially a half cycle of the input clock signal;
- a first logic gate configured to generate the first clock signal by performing a first logic operation on the third and fifth clock signals;
- and
- a second logic gate configured to generate the second clock signal by performing a second logic operation on the fourth and sixth clock signals.
8 more elements
An apparatus, comprising:
- a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein the clock source comprises a tri-state ring oscillator comprising:
- a set of N+1 cascaded flip-flops including respective clock inputs configured to receive the input clock signal;
- and
- an inverting multiplexer including a first input coupled to a data output of the (N−1)th cascaded flip-flop, a second input coupled to a data output of the Nth cascaded flip-flop, an output coupled to a data input of the 0th cascaded flip-flop, and a select input coupled to a data output of the ((N−1)/2)th cascaded flip-flop if N is odd or the (N/2)th cascaded flip-flop if N is even;
- wherein the first clock signal is based on a clock signal at the data output of the ((N−1)/2)th cascaded flip-flop if N is odd or the (N/2)th cascaded flip-flop if N is even;
- and
- wherein the second clock signal is based on a clock signal at the data output of the Nth cascaded flip-flop.
7 more elements
An apparatus, comprising:
- a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein the clock source comprises a 2N modulo counter configured to generate a first set of m+1 clock signals sequentially numbered from zero (0) to m, wherein 2m+1 is greater than 2N+1, wherein the first and second clock signals are based on the mth clock signal;
- wherein the 2N modulo counter comprises:
- a set of m+1 combinational logic circuits, each including inputs configured to receive and perform a logic operation on the first set of m+1 clock signals, to generate a second set of m+1 clock signals, respectively;
- and
- a set of m+1 flip-flops including:
- data inputs configured to receive the second set of m+1 clock signals, respectively;
- data outputs configured to generate the first set of m+1 clock signals, respectively;
- and clock inputs configured to receive the input clock signal.
8 more elements
An apparatus, comprising:
- a clock source configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- a logic circuit configured to perform a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein the clock source comprises a 2N modulo counter configured to generate a first set of m+1 clock signals sequentially numbered from zero (0) to m, wherein 2m+1 is greater than 2N+1, wherein the first and second clock signals are based on the mth clock signal;
- wherein the clock source comprises a shifted clock signal generator configured to generate a shifted clock signal based on the (m−1)th and mth clock signals, wherein a phase difference between the shifted clock signal and the mth clock signal is substantially (N+1)/2 cycles of the input clock signal if N is odd or N/2 cycles of the input clock signal if N is even, wherein the first and second clock signals are based on the mth and shifted clock signals, respectively.
2 more elements
A method, comprising:
- generating first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- performing a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein generating the first and second clock signals comprises:
- generating a set of m+1 clock signals sequentially numbered from zero (0) to m, wherein 2m+1 is greater than 2N+1;
- and
- generating a shifted clock signal based on the (m−1)th clock signal and the mth clock signal, wherein a phase difference between the mth clock signal and the shifted clock signal is substantially (N+1)/2 cycles of the input clock signal if N is odd or substantially N/2 cycles of the input clock signal if N is even, wherein the first and second clock signals are based on the mth clock signal and the shifted clock signal, respectively.
4 more elements
An apparatus, comprising:
- means for generating first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- means for performing a logic operation on the first and second clock signals to generate an output clock signal with a frequency being substantially the frequency of the input clock signal divided by NP5, where P5 is a half fraction;
- wherein the means for generating the first and second clock signals is configured to:
- generate a set of m+1 clock signals sequentially numbered from zero (0) to m, wherein 2m+1 is greater than 2N+1;
- and
- generate a shifted clock signal based on the (m−1)th clock signal and the mth clock signal, wherein a phase difference between the mth clock signal and the shifted clock signal is substantially (N+1)/2 cycles of the input clock signal if N is odd or substantially N/2 cycles of the input clock signal if N is even, wherein the first and second clock signals are based on the mth clock signal and the shifted clock signal, respectively.
4 more elements
An apparatus, comprising:
- a clock source including an input configured to generate first and second clock signals based on an input clock signal, wherein each of the first and second clock signals has a frequency being substantially a frequency of the input clock signal divided by 2N+1, where N is an integer;
- and
- a logic circuit including first and second inputs coupled to first and second outputs of the clock source, respectively, and an output configured to generate an output clock signal with a frequency being substantially a frequency of the input clock signal divided by NP5, where N is an integer and P5 is a half fraction;
- wherein the clock source is configured to:
- generate a set of m+1 clock signals sequentially numbered from zero (0) to m, wherein 2m+1 is greater than 2N+1;
- and
- generate a shifted clock signal based on the (m−1)th clock signal and the mth clock signal, wherein a phase difference between the mth clock signal and the shifted clock signal is substantially (N+1)/2 cycles of the input clock signal if N is odd or substantially N/2 cycles of the input clock signal if N is even, wherein the first and second clock signals are based on the mth clock signal and the shifted clock signal, respectively.
4 more elements
Dependencies are inferred from the claim text.