Injection current modulation for chirp signal timing control
AssigneeNXP B.V.
InventorsPiotr Gibas, Tarik Saric
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Abstract
A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.
Claims20
A method, comprising:
- calibrating an injection current of a chirp injection current profile by providing a calibration ramp of a dummy chirp to a first set of capacitors of a capacitor bank of a phase-locked loop (PLL) during a calibration phase of the PLL, wherein the capacitor bank is coupled to a buffer configured to output a buffer current that is used to calibrate the injection current of the chirp injection current profile;
- and
- generating a frequency chirp based on the chirp injection current profile during an acquisition phase of the PLL.
A frequency chirp signal generator configured to provide a frequency-modulated continuous-wave (FMCW) signal, the frequency chirp signal generator comprising:
- a chirp timing engine configured to calibrate an injection current supplied to a first set of capacitors of a capacitor bank of a phase-locked loop (PLL) during a calibration phase of the PLL, wherein the capacitor bank is coupled to a buffer configured to output a buffer current that is used to calibrate the injection current;
- and
- an injection digital to analog converter (DAC) configured to generate the calibrated injection current during a chirp sequence.
A phase-lock loop (PLL) circuit configured to generate a frequency chirp for a frequency-modulated continuous-wave (FMCW) signal generator, comprising:
- a chirp timing engine configured to generate a chirp injection current profile supplied to a first set of capacitors of a capacitor bank of a phase-locked loop (PLL) during a calibration phase of the PLL, wherein the capacitor bank is coupled to a buffer configured to output a buffer current that is used to generate the chirp injection current profile;
- and
- an injection digital to analog converter (DAC) configured to generate a calibrated injection current supplied to the first set of capacitors based on the chirp injection current profile at the PLL during a chirp sequence.
Dependencies are inferred from the claim text.