An electronic device, comprising a logic operation circuit, the logic operation circuit comprising:
- at least one differential logic operation circuit, comprising:
- a logic network module, comprising a first logic network unit and a second logic network unit with functions complementary to each other;
- a differential signal generated based on input signals of the first logic network unit and the second logic network unit, the first logic network unit and the second logic network unit performing a predetermined logic function to output an operation result based on the input signals;
- and
- a differential amplifier module, comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal and the second input terminal being connected to an output of the first logic network unit and the second logic network unit respectively;
- the first output terminal and the second output terminal forming a differential output terminal to amplify the operation result to obtain and output a logic operation result;
- wherein, the differential amplifier module comprises:
- a differential amplifier unit connected to an output terminal of the logical network module, and configured to amplify the operation result and output the logic operation result;
- a pre-charging unit connected to the differential amplifier unit, and configured to pre-charge the differential amplifier module for controlling a voltage of the differential output terminal to be a supply voltage in a pre-charging unit, and
- a current source unit, connected to the differential amplifier unit, and configured to establish a current path for the differential amplifier unit during an evaluation period;
- wherein, the differential amplifier module further comprises a storage unit, connected with output terminals of the first logic network unit and a second logic network unit, and configured to store information;
- wherein, the differential amplifier module further comprises an absorbing unit connected to the storage unit, and configured to absorb excess electric charges generated by the storage unit when switching;
- wherein, the current source unit comprises a transistor M1, a transistor M2, and a capacitor C, the transistor M1 and the transistor M2 are N-channel MOSFETs, with a gate terminal of the transistor M1 connected to a clock signal CLK, a source terminal connected to a drain terminal of the transistor M2 and one end of capacitor C, a gate terminal of the transistor M2 connected to a clock signal CLK, and the phase of the clock signal CLK is opposite to that of clock signal CLK, a source terminal of the transistor M2 is grounded.